Semiconductor memory device

ABSTRACT

According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a Continuation of U.S. application Ser. No. 14/014,183, filedAug. 29, 2013, which is based upon and claims the benefit of U.S.Provisional App. No. 61/804,548, filed Mar. 22, 2013, the entirecontents of both of which are incorporated herein by reference.

FIELD

Embodiments of the present invention relate to a semiconductor memorydevice.

BACKGROUND

In a semiconductor memory device such as an SDRAM, access is performedby, for example, inputting a row address together with an active commandand inputting a column address together with a read command/writecommand. However, in recent years, the size of addresses (the number ofbits) has been increased as the storage capacity of a semiconductormemory device increases.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an MRAM according to a first embodiment;

FIG. 2 is a circuit diagram of a memory cell array and a redundancyarea;

FIG. 3 is a circuit diagram of a fuse box and a redundancy judgmentcircuit;

FIG. 4 is a cross-sectional view of an MTJ element;

FIG. 5 is a timing chart showing operation of the MRAM;

FIG. 6 is a timing chart showing operation of an MRAM according to asecond embodiment; and

FIG. 7 is a circuit diagram of a fuse box and a redundancy judgmentcircuit.

DETAILED DESCRIPTION

In general, according to one embodiment, there is provided asemiconductor memory device comprising:

a memory cell array comprising memory cells;

a redundancy area comprising redundancy cells which are used for failurecells in the memory cell array;

first word lines connected to the memory cell array;

second word lines connected to the redundancy area;

a first row decoder configured to perform selecting from the first wordlines based on a row address;

a judgment circuit configured to determine whether or not a replacementoperation with the redundancy area is needed based on a redundancyaddress included in the row address; and

a second row decoder configured to perform selecting from the secondword lines based on a determination result by the judgment circuit,

wherein the row address includes a first row address and a second rowaddress input in order in a time-sharing method, and

the first row address includes all of the redundancy address.

Embodiments of the present invention will be described below withreference to the drawings. In the description below, components with thesame functions and configurations are denoted by the same referencenumerals, and duplicate descriptions are provided only when needed.

The embodiments will be described below taking an MRAM (Magnetic RandomAccess Memory) as an example of a semiconductor memory device.

[First embodiment]

[1. Configuration of the MRAM]

[1-1. General configuration of the MRAM]

FIG. 1 is a block diagram of an MRAM 10 according to a first embodiment.The MRAM 10 comprises a memory cell array 11, a redundancy area 12, asense amplifier (S/A) 13 serving as a read circuit, a write driver (W/D)14 serving as a write circuit, an ECC (Error Checking and Correcting)circuit 15, a page buffer (P/B) 16, an input/output circuit 17, a normalrow decoder 18, a redundancy row decoder 19, a fuse box 20 serving as afailure address storage unit, a redundancy judgment circuit 21, acontroller 22, a row address buffer 23, a column address buffer 24, andan address receiver 25.

The memory cell array 11 comprises a plurality of memory cells arrangedin a matrix. The memory cell array 11 comprises a plurality of wordlines (normal word lines) NWL <0:m>, a plurality of bit lines, and aplurality of source lines disposed therein. One word line NWL and onepair of a bit line and a source line are connected to one memory cell.

The redundancy area 12 is provided to repair failure memory cellsoccurring in the memory cell array 11. The redundancy area 12 has asmaller storage capacity than the memory cell array 11 but has the sameconfiguration as that of the memory cell array 11. That is, theredundancy area 12 comprises a plurality of redundancy cells arranged ina matrix. Each of the redundancy cells has the same configuration asthat of the memory cell. The redundancy area 12 comprises a plurality ofword lines (redundancy word lines) RWL<0:n> arranged therein, and aplurality of bit lines and source lines arranged therein and which arecommon to the memory cell array 11. One word line RWL and one pair of abit line and a source line are connected to one redundancy cell. Theredundancy area 12 is replaced with the memory cell array 11 in units ofone row (a group of memory cells connected to one word line RWL) or aplurality of rows.

The address receiver 25 receives an address ADD, a clock CLK, and a chipselect signal CS from an external circuit. The address ADD includes arow address RA and a column address CA. The address ADD and the chipselect signal CS are sent to the controller 22. The row address RA issent to the row address buffer 23. The column address CA is sent to thecolumn address buffer 24.

The column address buffer 24 receives the column address CA from theaddress receiver 25. The column address buffer 24 sends the columnaddress CA to the sense amplifier 13, the write driver 14, the pagebuffer 16, and the input/output circuit 17.

The row address buffer 23 receives the row address RA from the addressreceiver 25. The row address buffer 23 sends a row address RA<0:a> tothe normal row decoder 18, and sends a redundancy row address RA<x:y> tothe redundancy judgment circuit 21. The redundancy row address RA<x:y>comprises a part of the row address RA<0:a>.

The normal row decoder 18 is connected to a plurality of word linesNWL<0:m> disposed in the memory cell array 11. The normal row decoder 18selects any one of the plurality of word lines NWL<0:m> based on the rowaddress RA<0:a>.

The redundancy row decoder 19 is connected to a plurality of word linesRWL<0:n> disposed in the redundancy area 12. The redundancy row decoder19 selects any one of the plurality of word lines RWL<0:n> based on asignal HIT<0:n> sent from the redundancy judgment circuit 21.

The fuse box 20 stores addresses (failure addresses) for use inidentifying word lines connected to failure memory cells occurring inthe memory cell array 11. The fuse box 20 comprises a plurality of fuseelements configured to store failure addresses. A specific configurationof the fuse box 20 will be described below.

The redundancy judgment circuit 21 compares the redundancy row addressRA<x:y> with each of the failure addresses stored in the fuse box 20 togenerate a signal HIT<0:n> and a signal HITSUMB as a result of thecomparison. The signal HIT<0:n> is sent to the redundancy judgmentcircuit 21. The signal HITSUMB is sent to the normal row decoder 18. Aspecific configuration of the redundancy judgment circuit 21 will bedescribed below.

The sense amplifier 13 is connected to a plurality of bit lines. Forexample, in the case of a voltage detection scheme, the sense amplifier13 compares a reference voltage with a cell voltage applied to aselected memory cell via the corresponding bit line BL to detect andamplify data in the selected memory cell. The write driver 14 isconnected to a plurality of bit lines and a plurality of source lines.The write driver 14 writes data to the selected memory cell via theappropriate bit line and source line.

The page buffer 16 holds write data sent from the input/output circuit17 and read data sent from the sense amplifier 13.

The input/output circuit 17 is connected to an external circuit to carryout a process of outputting and receiving data to and from the externalcircuit. The input/output circuit 17 sends input data received from theexternal circuit to the page buffer as write data. The input/outputcircuit 17 outputs read data received from the page buffer 16 to theexternal circuit as output data.

The controller 22 integrally controls the operation of the MRAM 10. Thecontroller 22 receives the clock CLK from the external circuit. Thecontroller 22 supplies various control signals to the sense amplifier13, the write driver 14, the page buffer 16, and the input/outputcircuit 17 to control the operations of these circuits.

[1-2. Configuration of the memory cell array and the redundancy area]

Now, a configuration of the memory cell array 11 and the redundancy area12 will be described. FIG. 2 is a circuit diagram of the memory cellarray 11 and the redundancy area 12. The memory cell array 11 comprisesa plurality of memory cells MC arranged in a matrix. The memory cellarray 11 comprises a plurality of word lines NWL<0:m>, a plurality ofbit lines BL<0:i>, and a plurality of source lines SL<0:i>. The memorycell MC is connected to one word line NWL and one pair of a bit line BLand a source line SL.

The memory cell MC comprises a magnetoresistive effect element (MTJ(Magnetic Tunnel Junction) element) 30 and a select transistor 31. Theselect transistor 31 comprises, for example, an N-channel MOSFET. Oneend of the MTJ element 30 is connected to the corresponding bit line BL.The other end of the MTJ element 30 is connected to a drain of theselect transistor 31. A gate of the select transistor 31 is connected tothe corresponding word line NWL. A source of the select transistor 31 isconnected to the corresponding source line SL.

The redundancy area 12 comprises a plurality of redundancy cells RCarranged in a matrix. The redundancy area 12 comprise a plurality ofword lines RWL<0:n>, a plurality of bit lines BL<0:i>, and a pluralityof source lines SL<0:i>. The redundancy cell RC is connected to one wordline RWL and one pair of a bit line BL and a source line SL. Theredundancy cell RC has the same configuration as that of the memory cellMC.

[1-3. Configuration of the fuse box and the redundancy judgment circuit]

Now, an example of configuration of the fuse box 20 and the redundancyjudgment circuit 21 will be described. FIG. 3 is a circuit diagram ofthe fuse box 20 and the redundancy judgment circuit 21.

The fuse box 20 comprises a plurality of fuse sets FS<0:n> correspondingto the plurality of word lines RWL<0:n>. Each of the fuse sets FScomprises a plurality of fuse units 50 corresponding to the number ofbits in the redundancy row address RA<x:y> and one enable fuse unit 51.Each of the fuse units 50 comprises a fuse element 50A and a comparator50B. The fuse element 50A is, for example, a laser fuse (electric fuse).The enable fuse unit 51 also has the same configuration as that of thefuse unit 50.

The enable fuse unit 51 is used to determine whether or not to use thefuse set FS including this enable fuse unit 51. Information indicatingwhether or not to use the fuse set FS is programmed in the fuse elementin the enable fuse unit 51. The enable fuse unit 51 is configured tooutput “H” if the fuse set FS is to be used.

An address (failure address) for use in identifying a word lineconnected to a failure memory cell included in the memory cell array 11(that is, one of the word lines in the memory cell array 11 which is tobe replaced with the redundancy area 12) is programmed in each of theplurality of fuse elements 50A included in the plurality of fuse units50 in each fuse set FS. The fuse unit 50 (specifically, the comparator50B) compares an address bit input to the fuse unit 50 itself with a bitstored in the fuse element 50A. If the address bit matches the storedbit, the fuse unit 50 outputs “H”.

The redundancy judgment circuit 21 comprises a plurality of (forexample, two) NAND gates 52A and 52B connected to each fuse set FS and aNOR gate 53 connected to outputs of the NAND gates 52A and 52B. Theredundancy judgment circuit 21 further comprises a NOR gate 54 connectedto outputs of a plurality of NOR gates 53<0:n> corresponding to aplurality of word lines RWL<0:n>.

If the failure address stored in the fuse set FS<0> matches theredundancy row address RA<x:y>, the redundancy judgment circuit 21asserts a signal HIT<0> (outputs “H”). The signal HIT<1:n> operatessimilarly to the signal HIT<0>. The signal HIT<0:n> is sent to theredundancy row decoder 19. Finally, the redundancy word line RWL<α>corresponding to the asserted signal HIT<α> is activated.

Furthermore, if any of the signals HIT<0:n> is asserted, the redundancyjudgment circuit 21 asserts the signal HITSUMB (outputs “L”). The signalHITSUMB is sent to the normal row decoder 18. The signal HITSUMB at the“L” level means that an operation of replacement with the redundancyarea 12 is to be performed. Hence, if the signal HITSUMB is at the “L”level, the normal row decoder 18 operates to avoid activating the wordline NWL<0:m>.

[1-4. Structure of the MTJ element]

Now, an example of the structure of the MTJ element 30 will bedescribed. FIG. 4 is a cross-sectional view of the MTJ element 30. TheMTJ element comprises a lower electrode 40, a memory layer (alsoreferred to as a free layer) 41, a nonmagnetic layer (tunnel barrierlayer) 42, a reference layer (also referred to as a fixed layer) 43, andan upper electrode 44 stacked in this order. The order in which thememory layer 41 and the reference layer 43 are stacked may be reversed.

The memory layer 41 and the reference layer 43 are each formed of aferromagnetic material. The tunnel barrier layer 42 used is, forexample, an insulating material such as MGO.

Each of the memory layer 41 and the reference layer 43 has perpendicularmagnetic anisotropy and a direction of easy magnetization equal to aperpendicular direction. The memory layer 41 and the reference layer 43have a magnetization direction equal to an in-plane direction.

The memory layer 41 has a variable magnetization direction (themagnetization direction is inverted). The reference layer 43 has aninvariable magnetization direction (the magnetization direction isfixed). The reference layer 43 is set to have perpendicular magneticanisotropy energy sufficiently higher than the perpendicular magneticanisotropy energy of the memory layer 41. The magnetic anisotropy can beset by adjusting the composition of materials or film thicknesses. Amagnetization inversion current in the memory layer 41 is reduced asdescribed above such that a magnetization inversion current in thereference layer is larger than the magnetization inversion current inthe memory layer 41. Thus, the resultant MTJ element 30 comprises thememory layer 41 with a magnetization direction that is variable withrespect to a predetermined write current and the reference layer 43 witha magnetization direction that is invariable with respect to apredetermined write current.

The present embodiment uses a spin-transfer write scheme in which awrite current is passed directly through the MTJ element 30 to controlthe magnetization state of the MTJ element 30. The MTJ element 30 can beplaced in either a low resistance state or a high resistance statedepending on whether the correlation between the magnetization in thememory layer 41 and the magnetization in the reference layer 43 is in aparallel state or in an anti-parallel state.

When a write current flowing from the memory layer 41 toward thereference layer 43 is passed through the MTJ element 30, the correlationbetween the magnetization in the memory layer 41 and the magnetizationin the reference layer 43 is placed in the parallel state. In theparallel state, the MTJ element 30 has the lowest resistance value andis set to the low resistance state. The low resistance state of the MTJelement 30 is defined, for example, as data “0”.

On the other hand, when a write current flowing from the reference layer43 toward the memory layer 41 is passed through the MTJ element 30, thecorrelation between the magnetization in the memory layer 41 and themagnetization in the reference layer 43 is placed in the anti-parallelstate. In the anti-parallel state, the MTJ element 30 has the highestresistance value and is set to the high resistance state. The highresistance state of the MTJ element 30 is defined, for example, as data“1”.

Thus, the MTJ element 30 can be used as a storage element that can store1 bit data (binary data). The assignment of the resistance state and thedata for the MTJ element 30 can be optionally set.

Data is read from the MTJ element 30 by applying a read current to theMTJ element 30 and detecting the resistance value of the MTJ element 30based on a read current flowing through the MTJ element 30 during theapplication of the read voltage. The read current is set to a valuesufficiently smaller than a threshold beyond which magnetization isinverted by spin transfer.

[2. Operation]

Now, the operation of the MRAM 10 configured as described above will bedescribed. FIG. 5 is a timing chart showing the operation of the MRAM10. The MRAM 10 operates in synchronism with the clock CLK sent from theexternal circuit.

When the storage capacity of the memory cell array 11 grows to increasethe number of rows that can be specified by the row address RA in a dataread operation and a data write operation, the number of bits in the rowaddress RA correspondingly increases. Thus, in the present embodiment,the row address RA for use in selecting from the rows (word lines) inthe memory cell array 11 is divided into a first row address RA1 and asecond row address RA2, which are separately input to the MRAM 10 fromthe external circuit. That is, the first row address RA1 and the secondrow address RA2 are input from the external circuit to the MRAM 10 inthis order in a time-sharing method.

Furthermore, in the present embodiment, if the first row address RA1 isreceived, a redundancy determination operation is performed, andsubsequently, the second row address RA2 is received. When all of therow address RA<0:a> is obtained, operations other than the redundancydetermination operation which use the row address RA are performed.Thus, the first row address RA1 is configured to include the redundancyrow address RA<x:y>. The second row address RA2 comprises all of the rowaddress RA<0:a> except for the first row address RA1.

First, the controller 22 receives a pre-active command P-Act, and therow address buffer 23 receives the first row address RA1 from theexternal circuit. The pre-active command P-Act is input before an activecommand Act described below and used to input the first row address RA1to the MRAM 10. Subsequently, the row address buffer 23 sends the firstrow address RA1 to the fuse box 20 and the redundancy judgment circuit21.

Subsequently, the fuse box 20 and the redundancy judgment circuit 21perform a redundancy determination operation of determining whether ornot the failure address stored in the fuse set FS matches the redundancyrow address RA<x:y> included in the first row address RA1. Specifically,each fuse set FS compares the failure address stored in the fuseelements with the redundancy row address RA<x:y>. If the addressesmatch, the fuse set FS outputs a signal HIT at the “H” level, and if theaddresses fail to match, the fuse set FS outputs a signal HIT at the “L”level. The signal HIT is sent to the redundancy row decoder 19.

Moreover, if any of the signals HIT<0:n> is at the “H” level, theredundancy judgment circuit 21 outputs the signal HITSUMB at the “L”level. If all of the signals HIT<0:n> are at the “L” level, that is,replacement with the redundancy area 12 is not carried out, theredundancy area 12 outputs the signal HITSUMB at the “H” level. Thesignal HITSUMB is sent to the normal row decoder 18.

Subsequently, the controller 22 receives the active command Act from theexternal circuit. The row address buffer 23 receives the second rowaddress RA2 from the external circuit. The active command Act allowsexecution of a process of activating one (a selected word line) of aplurality of word lines in a selected bank and reading data from thememory cell array 11 to the page buffer 16. In actuality, one MRAM 10shown in FIG. 1 corresponds to one bank, and a plurality of banks aremounted on a substrate to form a nonvolatile memory. At this time, allof the row address RA<0:a>, comprising the first row address RA1 and thesecond row address RA2, is obtained. The row address RA<0:a> is thensent from the row address buffer 23 to the normal row decoder 18.

Subsequently, as long as the signal HITSUMB is at the “H” level, thenormal row decoder 18 uses the row address RA<0:a> to activate one ofthe word lines NWL<0:m>. If the selected word line is failure (thesignal HITSUMB is at the “L” level), the word line is replaced with theredundancy area 12. Specifically, the redundancy decoder 19 activatesone of the word lines RWL<0:n> based on the signal HIT<0:n>.Subsequently, the sense amplifier 13 reads data from the memory cellarray 11. The read data is written to the page buffer 16 via the ECCcircuit 15.

Subsequently, the controller 22 receives a read command or a writecommand (R/W) from the external circuit. The column address buffer 24receives a column address CA from the external circuit. Thereafter, thecontroller 22 performs a read operation or a write operation on thecolumn designated by the column address CA.

[Effects]

As described above in detail, the first embodiment is as follows. Thefirst row address RA1 and the second row address RA2, included in therow address RA, are input to the MRAM 10 in this order in a time-sharingmethod. The first row address RA1, which is input earlier, is configuredto include all of the redundancy address related to a redundancyreplacement operation. Then, the redundancy replacement operation isstarted immediately after the reception of the first row address RA1.

Thus, the first embodiment allows a redundancy determination operationto be performed before the active command Act is received, enabling anapparent reduction in time required for the redundancy determination.This enables a reduction in a delay time tRCD (RAS to CAS delay) fromthe reception of the active command Act until the reception of the readcommand or the write command, thus increasing the operating speed of theMRAM 10.

[Second embodiment]

According to a second embodiment, the row address RA for use inselecting from the rows (word lines) in the memory cell array 11 isdivided into the first row address RA1 and the second row address RA2.The first row address RA1 and the second row address RA2 are separatelyinput to the MRAM 10 from the external circuit. That is, the first rowaddress RA1 and the second row address RA2 are input from the externalcircuit to the MRAM 10 in this order in a time-sharing method.

Furthermore, according to the present embodiment, the first row addressRA1 is configured to include a part of the redundancy row addressRA<x:y>. The second row address RA2 comprises all of the row addressRA<0:a> except for the first row address RA1. That is, the second rowaddress RA2 also includes a part of the redundancy row address RA<x:y>.After the first row address RA1 is received, a part of the redundancydetermination operation is performed. Subsequently, upon receiving thesecond row address RA2 to obtain all of the row address RA<0:a>, theMRAM performs all of the remaining part of the redundancy determinationoperation and the operations other than the redundancy determinationoperation which use the row address RA.

FIG. 6 is a timing chart showing the operation of the MRAM 10 accordingto the second embodiment. First, the controller 22 receives thepre-active command P-Act from the external circuit, and the row addressbuffer 23 receives the first row address RA1 from the external circuit.Then, the row address buffer 23 sends the first row address RA1 to thefuse box 20 and the redundancy determination circuit 21.

Subsequently, the fuse box 20 and the redundancy judgment circuit 21perform a redundancy determination operation of determining whether ornot the failure address stored in the fuse set FS matches a part of theredundancy row address RA<x:y> included in the first row address RA1,that is, the fuse box 20 and the redundancy judgment circuit 21 performa part of the redundancy determination operation (“PD op1” in FIG. 6).

Subsequently, the controller 22 receives the active command Act from theexternal circuit. The row address buffer 23 receives the second rowaddress RA2 from the external circuit. At this time, all of the rowaddress RA<0:a>, comprising the first row address RA1 and the second rowaddress RA2, is obtained and sent from the row address buffer 23 to thenormal row decoder 18. Furthermore, all of the remaining part of theredundancy row address RA<x:y> is sent from the row address buffer 23 tothe fuse box 20 and the redundancy judgment circuit 21.

Subsequently, the fuse box 20 and the redundancy judgment circuit 21 usethe redundancy row address RA<x:y> to perform all of the remaining partof the redundancy determination operation (“RD op2” in FIG. 6).

Subsequently, the normal row decoder 18 uses the row address RA<0:a> toactivate the selected word line. If the selected word line is failure,the word line is replaced with the redundancy area 12. Thereafter, thesense amplifier 13 reads data from the memory cell array 11, and theread data is written to the page buffer 16 via the ECC circuit 15. Thesubsequent operation is the same as the corresponding operation in thefirst embodiment.

(Example of configuration of the fuse box 20 and the redundancy judgmentcircuit 21)

Now, an example of configuration of the fuse box 20 and the redundancyjudgment circuit 21 will be described. FIG. 7 is a circuit diagram ofthe fuse box 20 and the redundancy judgment circuit 21. A circuitportion of FIG. 7 corresponds to a critical path for the redundancydetermination operation. Reducing the time required for processing inthe circuit portion is important.

In the present embodiment, first fuse sets FS1<0:n> of the fuse setsFS<0:n> which correspond to the redundancy row address (a part of theredundancy row address RA<x:y>) included in the first row address RA1are collectively arranged at a short distance from one another.Furthermore, second fuse sets FS2<0:n> in the fuse sets FS<0:n> whichcorrespond to the redundancy row address (all of the remaining part ofthe redundancy row address RA<x:y>) included in the second row addressRA2 are collectively arranged at a short distance from one another.Moreover, the first fuse sets FS1<0:n> corresponding to the first rowaddress RA1, which is input earlier and involves a relatively sufficienttime for a calculation, are arranged away from a circuit (NOR gate53<0:n>) configured to calculate the signal HIT<0:n> and a circuit (NORgate 54) configured to calculate the signal HITSUMB. The second fusesets FS2<0:n> corresponding to the second row address RA1, which isinput later, are arranged closer to the NOR gate 53<0:n> and the NORgate 54 than the first fuse sets FS1<0:n>.

Thus, when the second row address RA2 is input, the redundancydetermination operation (“RD op1” in FIG. 7) related to the first rowaddress RA1 has already been completed. Consequently, the redundancydetermination operation (“RD op2” in FIG. 6) performed after the inputof the active command Act is only the arithmetic process related to thesecond fuse sets FS, arranged close to the NOR gate 54. This enables areduction in the time required for the redundancy determinationoperation performed after the inputting of the active command Act.

(Effects)

As described above in detail, according to the second embodiment, thefirst row address RA1 and the second row address RA2, included in therow address RA, are input to the MRAM 10 in this order in a time-sharingmethod. The first row address RA1, which is input earlier, is configuredto include a part of the redundancy address related to the redundancyreplacement operation. Then, the redundancy determination operation isstarted immediately after the reception of the first row address RA1.

Thus, the second embodiment allows a part of the redundancydetermination operation to be performed before the active command Act isreceived, enabling an apparent reduction in the time required for theredundancy determination. This enables a reduction in the delay timetRCD, thus increasing the operating speed of the MRAM 10.

Furthermore, the first fuse sets FS1<0:n> corresponding to the first rowaddress RA1 are arranged away from the circuit configured to calculatethe signal HIT<0:n> and the circuit configured to calculate the signalHITSUMB. An arithmetic process related to the first fuse sets FS1<0:n>is carried out earlier. This enables a further reduction in the timerequired for the redundancy determination operation related to thesecond row address RA2, which is input later.

Each of the above-described embodiments is configured to divide thewhole row address RA into two addresses and to input the addresses in atime-sharing method. However, the embodiments are not limited to thisconfiguration. The whole row address may be divided into three or moreaddresses, which are then input in a time-sharing method. In conjunctionwith this, the redundancy row address may be divided into two or moreaddresses before input.

Furthermore, each of the above-described embodiments takes the MRAM asan example of the semiconductor memory device. However, the embodimentsare not limited to the MRAM but are applicable to any other memory suchas an SDRAM (Synchronous DRAM).

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A semiconductor memory device comprising: amemory cell array comprising memory cells; and a redundancy areacomprising redundancy cells which are used for failure cells in thememory cell array; wherein: the semiconductor memory device receives anaddress from outside, the address includes a first portion, a secondportion, and a third portion which are input in order and divided fromeach other, the first portion includes a redundancy address for theredundancy area, the first portion is input with a command, and a firsttime interval between the first portion and the second portion isdifferent from a second time interval between the second portion and thethird portion.
 2. The device of claim 1, wherein the first time intervalbetween the first portion and the second portion is shorter than thesecond time interval between the second portion and the third portion.3. The device of claim 1, wherein the first portion, the second portion,and the third portion are input in a time-sharing method.
 4. The deviceof claim 1, further comprising a judgment circuit which determineswhether or not a replacement operation with the redundancy area isneeded based on the redundancy address.
 5. The device of claim 4,wherein the judgment circuit starts a determination operation after thefirst portion is input.
 6. The device of claim 4, further comprisingfuse sets which store failure addresses identifying the failure cells inthe memory cell array, wherein the judgment circuit determines whetheror not the redundancy address matches one of the failure addressesstored in the fuse sets.
 7. The device of claim 1, further comprising adecoder which decodes the address.
 8. The device of claim 1, whereineach of the memory cells comprises a magnetoresistive effect element. 9.A semiconductor memory device comprising: a memory cell array comprisingmemory cells; and a redundancy area comprising redundancy cells whichare used for failure cells in the memory cell array, wherein: thesemiconductor memory device receives an address from outside, theaddress includes a first portion, a second portion, and a third portionwhich are input in order and divided from each other, the first portionincludes a redundancy address for the redundancy area, the first portionis input with a command, and a number of cycles between the firstportion and the second portion is different from a number of cyclesbetween the second portion and the third portion.
 10. The device ofclaim 9, wherein the number of cycles between the first portion and thesecond portion is shorter smaller than the number of cycles between thesecond portion and the third portion.
 11. The device of claim 9, whereinthe first portion, the second portion, and the third portion are inputin a time-sharing method.
 12. The device of claim 9, further comprisinga judgment circuit which determines whether or not a replacementoperation with the redundancy area is needed based on the redundancyaddress.
 13. The device of claim 12, wherein the judgment circuit startsa determination operation after the first portion is input.
 14. Thedevice of claim 12, further comprising fuse sets which store failureaddresses identifying the failure cells in the memory cell array,wherein the judgment circuit determines whether or not the redundancyaddress matches one of the failure addresses stored in the fuse sets.15. The device of claim 9, further comprising a decoder which decodesthe address.
 16. The device of claim 9, wherein each of the memory cellscomprises a magnetoresistive effect element.
 17. A semiconductor memorydevice comprising: a memory cell array comprising memory cells; and aredundancy area comprising redundancy cells which are used for failurecells in the memory cell array, wherein: the semiconductor memory devicereceives an address from outside, the address includes a first portion,a second portion, and a third portion which are input in order anddivided from each other, the first portion includes a redundancy addressrelated to a redundancy replacement operation, the first portion isinput with a command, and a first time interval between the firstportion and the second portion is different from a second time intervalbetween the second portion and the third portion.
 18. The device ofclaim 17, wherein the first time interval between the first portion andthe second portion is shorter than the second time interval between thesecond portion and the third portion.
 19. The device of claim 17,wherein the first portion, the second portion, and the third portion areinput in a time-sharing method.
 20. The device of claim 17, furthercomprising a judgment circuit which determines whether or not areplacement operation with the redundancy area is needed based on theredundancy address.
 21. The device of claim 20, wherein the judgmentcircuit starts a redundancy determination operation after the firstportion is input.
 22. The device of claim 20, further comprising fusesets which store failure addresses identifying the failure cells in thememory cell array, wherein the judgment circuit determines whether ornot the redundancy address matches one of the failure addresses storedin the fuse sets.
 23. The device of claim 17, wherein the second portionincludes a redundancy address related to a redundancy replacementoperation.
 24. The device of claim 17, further comprising a decoderwhich decodes the address.
 25. The device of claim 17, wherein each ofthe memory cells comprises a magnetoresistive effect element.
 26. Asemiconductor memory device comprising: a memory cell array comprisingmemory cells; and a redundancy area comprising redundancy cells whichare used for failure cells in the memory cell array, wherein: thesemiconductor memory device receives an address from outside, theaddress includes a first portion, a second portion, and a third portionwhich are input in order and divided from each other, the first portionincludes a redundancy address related to a redundancy replacementoperation, the first portion is input with a command, and a number ofcycles between the first portion and the second portion is differentfrom a number of cycles between the second portion and the thirdportion.
 27. The device of claim 26, wherein the number of cyclesbetween the first portion and the second portion is smaller than thenumber of cycles between the second portion and the third portion. 28.The device of claim 26, wherein the first portion, the second portion,and the third portion are input in a time-sharing method.
 29. The deviceof claim 26, further comprising a judgment circuit which determineswhether or not a replacement operation with the redundancy area isneeded based on the redundancy address.
 30. The device of claim 29,wherein the judgment circuit starts a redundancy determination operationafter the first portion is input.
 31. The device of claim 29, furthercomprising fuse sets which store failure addresses identifying thefailure cells in the memory cell array, wherein the judgment circuitdetermines whether or not the redundancy address matches one of thefailure addresses stored in the fuse sets.
 32. The device of claim 26,wherein the second portion includes a redundancy address related to aredundancy replacement operation.
 33. The device of claim 26, furthercomprising a decoder which decodes the address.
 34. The device of claim26, wherein each of the memory cells comprises a magnetoresistive effectelement.